FPGA I/O Features Help Lower Overall PCB Costs
by Dave Brady, Mentor Graphics Corp.

High-end FPGAs with embedded processors, DSP and memory blocks are now replacing entire ASICs. New device families have accelerated programming times by dedicating several general-purpose I/O pins to create wider configuration buses that can then revert back to their primary I/O functionality. Rising device complexities imply high pin counts, which bring about new challenges and added costs when integrating these devices on the PCB. Design teams must now implement changes to ensure they do not negate the cost and time-to-market benefits of using programmable logic in the first place.

The Growing I/O Complexity Challenge

FPGAs with 1000+ pin counts pose a problem when they are incorporated into the board schematic. Manually placing and connecting this multitude of pins is inefficient at best, especially when a minor modification in the FPGA design means time-consuming iterations in the board design. Despite rising pin counts, the pin pitches on the package have remained relatively constant, but pin densities on the PCB have significantly increased. The ensuing routing congestion implies that most PCB designers have to be highly skilled in high-density interconnect (HDI) manufacturing processes. The bottom line: PCBs containing FPGA devices with high pin counts create the need for more board layers at an additional 10% to 20% per layer of manufacturing costs.

Selecting and configuring the optimal I/O standard must be completed within the context of the PCB’s electrical characteristics. High-speed serial I/Os in new device families make interfacing between the FPGA and system board an extremely tricky problem. For example, multi-gigabit transceiver (MGT) technology is aimed at narrowing data paths significantly while dramatically increasing throughput. However, these high-speed I/Os bring new challenges. Instead of worrying about system timing, over/undershoot, crosstalk and proper termination, designer attention gets focused on issues such as dielectric loss, skin effects and deterministic/random jitter, and their impact on inter-symbol interference.

Three primary factors contribute to signal degradation and attenuation in differential, multi-gigabit signals. They are dielectric loss (as a function of length and board material), vias, and connector loss. Vias, depending on geometry, can contribute between 0.5-1.0 dB of loss per via, against total loss budgets that typically range from 10-15 dB. Thus, most FPGA manufacturers recommend that MGTs be placed along the FPGA’s perimeter to eliminate the need to drop vias down to internal signal layers. Careful stack-up planning is essential for these signals, achieving carefully calibrated differential impedance, per FPGA manufacturer specifications. [more]